INTEGRATED CIRCUITS DATA SHEET UCB1200 Advanced modem/audio analog front-end Product specification 1998 Jul 22 File under Integrated Circuits, Philips Semiconductors Product specification Advanced modem/audio analog front-end UCB1200 FEATURES * 48 pin LQFP (SOT313) small body SMD package and low external component count results in minimal PCB space requirement * 12-bit sigma delta audio codec with programmable sample rate, input and output voltage levels, capable of connecting directly to speaker and microphone, including digitally controlled mute, loopback and clip detection functions * 14-bit sigma delta telecom codec with programmable sample rate, including digitally controlled input voltage level, mute, loopback and clip detection functions. The telecom codec can be directly connected to a Data Access Arrangement (DAA) and includes a built in sidetone suppression circuit * Complete 4 wire resistive touch screen interface circuit supporting position, pressure and plate resistance measurements * 10-bit successive approximation ADC with internal track and hold circuit and analog multiplexer for touch screen read-out and monitoring of four external high voltage (7.5V) analog voltages * High speed, 4 wire serial interface data bus (SIB) for communication to the system controller * 3.3V supply voltage and built in power saving modes make the 9397 750 04055 optimal for portable and battery powered applications * Maximum operating current 25 mA * 10 general purpose IO pins APPLICATIONS * Handheld Personal Computers, Personal Intelligent Communicators, Personal Digital Assistants * Smart Mobile Phones * Screen/Web Phones * Internet Access Terminal * Modems GENERAL DESCRIPTION The UCB1200 is a single chip, integrated mixed signal audio and telecom codec. The single channel audio codec is designed for direct connection of a microphone and a speaker. The built-in telecom codec can directly be connected to a DAA and supports high speed modem protocols. The incorporated analog to digital converter and the touch screen interface provides complete control and read-out of an 4 wire resistive touch screen. The 10 general purpose I/O pins provide programmable inputs and/or outputs to the system. The UCB1200 has a serial interface bus (SIB) intended to communicate to the system controller. Both the codec input data and codec output data and the control register data are multiplexed on this SIB interface. 1998 Jul 22 2 853-2052 19059 Philips Semiconductors Product specification Advanced modem/audio analog front-end UCB1200 ORDERING INFORMATION TYPE PACKAGE NUMBER NAME DESCRIPTION VERSION UCB1200BE LQFP48 plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm SOT313-2 BLOCK DIAGRAM IO(n) down Digital IO TINP 1 bit sample circuits Serial bus SIBDIN ADC filter interface SIBDOUT TINN SIBSYNC up data / IRQOUT TOUTP 4 bit sample control DAC filter registers TOUTN Clock buffers & sample rate SIBCLK dividers down MICP 1 bit sample Voltage ADC filter reference touch MICGND screen interface up SKRP 4 bit sample DAC 10 bit ADC filter SKRN multiplexer TSPX,TSMX AD(n) TSPY,TSMY Fig.1 Block diagram. 1998 Jul 22 3 Philips Semiconductors Product specification Advanced modem/audio analog front-end UCB1200 PINNING SYMBOL PIN DESCRIPTION RESET STATE TYPE(1) IO7 1 general purpose I/O pins input I/OC IO8 2 general purpose I/O pins input I/OC IO9 3 general purpose I/O pins input I/OC ADCSYNC 4 ADC synchronization pulse input - IC VSSD 5 digital ground - S(2) n.c 6 not connected - - VSSA2 7 analog speaker driver ground - S SKPRN 8 negative speaker output hi Z OA SPRKP 9 positive speaker output hi Z OA VDDA2 10 analog speaker driver supply - S TOUTP 11 positive telecom codec output hi Z OA TOUTN 12 negative telecom codec output hi Z OA TEST 13 test mode protection `0' IC TINN 14 negative telecom codec input hi Z IA TINP 15 positive telecom codec input hi Z IA VREFBYP 16 external reference voltage input hi Z I/OA VDDA1 17 analog supply - S VSSA1 18 analog ground - S n.c 19 not connected - - MICGND 20 microphone ground switch input hi Z IA MICP 21 microphone signal input hi Z IA AD3 22 analog voltage inputs hi Z IA AD2 23 analog voltage inputs hi Z IA AD1 24 analog voltage inputs hi Z IA AD0 25 analog voltage inputs hi Z IA VSSA3 26 analog touch screen ground - S TSPY 27 positive Y-plate touch screen hi Z I/OA TSMX 28 negative X-plate touch screen hi Z I/OA TSMY 29 negative Y-plate touch screen hi Z I/OA TSPX 30 positive X-plate touch screen hi Z I/OA n.c 31 not connected - - VDDD 32 digital supply - S IO0 33 general purpose I/O pins input I/OC IO1 34 general purpose I/O pins input I/OC IO2 35 general purpose I/O pins input I/OC IO3 36 general purpose I/O pins input I/OC VSSD 37 digital ground - S RESET 38 asynchronous reset input - IC SIBSYNC 39 SIB synchronization input - IC 1998 Jul 22 4 Philips Semiconductors Product specification Advanced modem/audio analog front-end UCB1200 SYMBOL PIN DESCRIPTION RESET STATE TYPE(1) SIBDOUT 40 SIB data output `1'(6) OC SIBCLK 41 SIB serial interface clock - IC SIBDIN 42 SIB data input - IC IRQOUT 43 interrupt output `0' OC n.c 44 not connected - - IO4 45 general purpose I/O pins input I/OC IO5 46 general purpose I/O pins input I/OC IO6 47 general purpose I/O pins input I/OC VDDD 48 digital supply - S Notes 1. I/OC = CMOS bidirectional; ID = digital input; S = supply; OA = analog output; IC = CMOS input; IA = analog input; I/OA = analog bidirectional; OC = CMOS output. 2. VSSD (pins 5 and 37) and VSSA1 (pin 18) are connected internally within the UCB1200. 3. SKPRN/SPKRP (pins 8 and 9), TINN/TINP (pins 14 and 15) and TOUTP/TOUTN are differential pairs 4. TEST (pin 13) is connected to an internal pull-down resistor. This pin should be held LOW during normal operation of the circuit. 5. The not connected pins (pins 6, 19, 31 and 44) are reserved for future applications and should be left floating. 6. SIBDOUT reset state is 1 until the SIB bus is running. SIBDOUT will be active once the SIB bus has started. 1998 Jul 22 5 Philips Semiconductors Product specification Advanced modem/audio analog front-end UCB1200 V DDD IO6 IO5 IO4 n.c. IRQOUT SIBDIN SIBCLK SIBDOUT SIBSYNC RESET V SSD dbook, full pagewidth 48 47 46 45 44 43 42 41 40 39 38 37 IO7 1 36 IO3 IO8 2 35 IO2 IO9 3 34 IO1 ADCSYNC 4 33 IO0 VSSD 5 32 VDDD n.c. 6 31 n.c. XXX UCB1200 VSSA2 7 30 TSPX SPKRN 8 29 TSMY SPRKP 9 28 TSMX VDDA2 10 27 TSPY TOUTP 11 26 VSSA3 TOUTN 12 25 AD0 13 14 15 16 17 18 19 20 21 22 23 24 MXXxxx n.c. TEST TINN TINP AD2 AD1 V DDA1 V SSA1 MICP AD3 VREFBYP MICGND Fig.2 Pin configuration. 1998 Jul 22 6 Philips Semiconductors Product specification Advanced modem/audio analog front-end UCB1200 FUNCTIONAL DESCRIPTION The UCB1200 consists of several analog and digital sub circuits which can be programmed via the Serial Interface Bus (SIB). This enables the user to set the UCB1200 functionality according to actual application requirements. AUDIO CODEC The audio codec contains an input channel, built up with an 64 times oversampling sigma delta analog to digital converter (ADC) with digital decimation filters and a programmable gain microphone preamplifier. The output path consists of a digital up sample filter, a 64 time oversampling 4 bit digital to analog converter (DAC) circuit followed by a BTL speaker driver, capable of driving a 16 speaker. The output path features a digital programmable attenuation and a mute function. The audio codec also incorporates a loopback mode, in which codec output path and the input path are connected in series. AUD_GAIN[4,3] AUD_OFF_CAN AUD_LOOP AUD_GAIN[2..0] 1bit ADC 12 MICP DIGITAL DECIMATION FILTER MICGND AUD_IN_ENA AUD_OUT_ENA VCCSPKR SPKRP 12 4bit DAC DIGITAL DIGITAL ATTENUATOR NOISE SHAPER SPKRN VSSSPKR AUD_MUTE AUD_ATT[2..0] AUD_ATT[4,3] Fig.3 Audio codec block diagram. 1998 Jul 22 7 Philips Semiconductors Product specification Advanced modem/audio analog front-end UCB1200 The audio sample rate (fsa) is derived from the SIB interface clock pin (SIBCLK) and is programmable through the SIB interface using AUD_DIV[n]. The audio sample rate is given by the following equation: (2 × f ) f SIBCLK = (8 < AUD_DIV[n] < 128) sa (64 × AUD_DIV[n]) -------------------------------------------------- For example, a serial clock of 9.216 MHz, with a divisor of 12, results in an audio sample rate of 24.0 kHz. Both the rising and the falling edges of SIBCLK are used in case AUD_DIV[n] is set to an odd number, which demands a 50% duty cycle of SIBCLK to obtain time equidistant sampling. PASSIVE ACTIVE UCB1200 UCB1200 VDDA1 VDDA1 17 17 MICP MICP 21 21 MICGND MICGND 20 20 VSSA1 VSSA1 18 18 Fig.4 Possible microphone connections. The UCB1200 audio codec input path accepts microphone signals directly, only a DC blocking capacitor is needed since the MICP input is biased around 1.4V. The `ground' side of the microphone is either connected to the analog ground (Vssa1) or to the MICGND pin. The latter will decrease the current consumption of active microphones, since the MICGND pin is made Hi-Z when the audio codec input path is disabled. The full scale input voltage of the audio input path is programmable in 1.5 dB steps by setting the appropriate number in AUDIO_GAIN[n] in the audio control register A. A clip detection circuit will inform the user whenever the input voltage exceeds the maximum input voltage, since this will lead to a high distortion. In that case AUD_CLIP_STAT in the audio control register B is set. When ACLIP_RIS_INT is set, an interrupt is generated on the IRQOUT pin on the rising edge of the clip detect signal. When ACLIP_FAL_INT is set, an interrupt is generated on the falling edge of the clip detect signal. The frequency response of the audio codec depends mainly on the selected sample rate, since the bandwidth is limited in the down and up sampling filters. These digital filters both contain several FIR and IIR low pass filters and a DC removal filter (high pass filter). A 3rd order smoothing filter is implemented in the DAC path, between DAC and speaker driver stage to reduce the spurious frequencies at the speaker outputs. 1998 Jul 22 8 Philips Semiconductors Product specification Advanced modem/audio analog front-end UCB1200 48dB 24dB 0dB 21dB 0dB 24dB 48dB 69dB programmed attenuation Fig.5 Analog and digital attenuation settings audio output path. The output level can be attenuated in 3 dB steps down to -69 dB. The first 8 attenuation steps (0 to 21 dB) are implemented in the analog domain. The digital up sample filter contains a 24 dB and a 48 dB attenuation setting. This arrangement preserves the resolution, thus the `audio quality' of the audio output signal for attenuation settings till 21 dB. The speaker driver is muted when AUDIO_MUTE in the audio control register B is set. The speaker driver will remain activated in that case, however no signal is produced by the speaker driver circuit. The speaker driver is designed to directly drive a bridge tied load (BTL). This yields the highest output power and this arrangement does not require external DC blocking capacitors. The speaker driver also accepts single ended connection of a speaker, in which case the maximum output power is reduced to a quarter of the BTL situation. Consequently this way of connecting the speaker to the speaker driver reduces the power consumption of the speaker driver in the UCB1200 by a factor of 2. Fig.6 shows possible ways to connect a speaker to the driver. Loading the amplifiers with a capacitive load may cause high frequency oscillations and should be done cautiously. 1998 Jul 22 9 Philips Semiconductors Product specification Advanced modem/audio analog front-end UCB1200 BRIDGE TIED SINGLE ENDED SPEAKER CONNECTIONS SPEAKER LOAD UCB1200 UCB1200 UCB1200 SPKRP SPKRP SPKRP 9 + 9 9 8 8 8 SPKRN SPKRN SPKRN + + + Fig.6 Possible speaker connections. The audio input and output path are activated independently; the input path is enabled when AUDIO_IN_ENA is set, the output path is enabled when AUD_OUT_ENA is set in the audio control register B. This provides the user the means to reduce the current consumption of the UCB1200 if one part of the audio codec is not used in the application. The audio codec has a loopback mode for system test purposes, which is activated when the AUDIO_LOOP bit in the audio control register B is set. This is an analog loopback which internally connects the output of the audio output path to the input of the audio input path, (see Fig.3). In this mode the normal microphone input is ignored, but the speaker driver can be operated normally. 1998 Jul 22 10 Philips Semiconductors Product specification Advanced modem/audio analog front-end UCB1200 TELECOM CODEC The telecom codec contains an input channel, built up from a 64 times oversampling sigma delta analog to digital converter (ADC) with digital decimation filters, programmable attenuation and built-in sidetone suppression circuit. The output path consist of a digital up sample filter, a 64 time oversampling 4 bit digital to analog converter (DAC) circuit followed by a differential output driver, capable of directly driving a 600 isolation transformer. The output path includes a mute function. The telecom codec also incorporates a loopback mode, in which codec output path and the input path are connected in series. TEL_SIDE_ENA TEL_LOOP TEL_ATT TINP 1bit ADC SIDETONE DIGITAL 14 SUPPRESSION DECIMATION TINN FILTER CIRCUIT TEL_IN_ENA TEL_OUT_ENA TOUTP 14 DIGITAL 4bit DAC NOISE TOUTN SHAPER TEL_MUTE Fig.7 Telecom codec block diagram. The telecom sample rate (fst) is derived from the SIB interface clock pin (SIBCLK) and is programmable through the SIB interface. The telecom sample rate is given by the following formula: (2 × F ) f SIBCLK = (15 < TEL_DIV[n] <128) st (64 × TEL_DIV[n]) -------------------------------------------------- For example, a SIBCLK of 9.216 MHz, with a divisor of 40, results in a telecom sample rate of 7.2 kHz. Both the rising and the falling edges of the SIBCLK are used in case TEL_DIV[n] is set to an odd number. In that case a 50% duty cycle of the SIBCLK signal is mandatory to obtain time equidistant sampling. The input path of the telecom codec has a programmable attenuation. It also implements a voice band filter, which consists of an digital low pass filter, which is a part of the decimation filter. Therefore the pass band of the voice band 1998 Jul 22 11 Philips Semiconductors Product specification Advanced modem/audio analog front-end UCB1200 filter is determined by the selected telecom codec sample rate. This voice band filter is activated by setting TEL_VOICE_ENA in the telecom control register B. The resulting telecom input filter curves are given in Fig.37 and Fig.38. The output section of the telecom codec is designed to interface with a 600 line through an isolation transformer. The built in mute function is activated by TEL_MUTE in the telecom control register B. The output driver remains active in the mute mode, however no output signal is produced. Loading the drivers with a capacitive load may cause high frequency oscillations and should be done cautiously. 1998 Jul 22 12 Philips Semiconductors Product specification Advanced modem/audio analog front-end UCB1200 TOUCH SCREEN MEASUREMENT MODES The UCB1200 contains an on chip interface for a 4 wire resistive touch screen. This interface supports three modes of touch screen measurements: position, pressure and plate resistance. POSITION MEASUREMENT Two position measurements are needed to determine the location of the pressed spot. First an X measurement, secondly a Y measurement. The X plate is biased during the X position measurement of the X plate and the voltage on one or both Y terminals (TSPY, TSMY) measured. The circuit can then be represented by a potentiometer, with the TSPY and/or TSMY electrode being the `wiper'. The measured voltage on the TSPY/TSMY terminal is proportional to the X position of the pressed spot of the touch screen. Vposition Vtscbias tspx tsmy tspy tsmx Fig.8 Touch screen setup for position measurement. In the Y position mode the X plate and Y plate terminals are interchanged, thus the Y plate is biased while the voltage on the TSPX and/or TSMX terminal is measured. 1998 Jul 22 13 Philips Semiconductors Product specification Advanced modem/audio analog front-end UCB1200 PRESSURE MEASUREMENT The pressure used to press the touch screen can be determined. In fact the contact resistance between the X and Y plate is measured, which is a good indication of the size of the pressed spot and the applied pressure. A soft stylus, e.g. a finger, leads to a rather large contact area between the two plates when a large pressure is applied. A hard stylus, e.g. a pen, leads to less variation in measured contact resistance since the contact area is rather small. Vtscbias ipressure tspx tsmy tspy tsmx Fig.9 Touch screen setup for pressure measurement. One plate is biased at one or both terminals during this pressure measurement, whereas the other plate is grounded, again on one or both terminals. The current flowing through the touch screen is a direct indication for the resistance between both plates. A compensation for the series resistance, formed by the touch screen plates itself will improve the accuracy of this measurement. 1998 Jul 22 14 Philips Semiconductors Product specification Advanced modem/audio analog front-end UCB1200 PLATE RESISTANCE MEASUREMENT The plate resistance of a touch screen varies typically a lot due to processing spread. Knowing the actual plate resistance makes it possible to compensate for the plate resistance effects in pressure resistance measurements. The plate resistance decreases when two or more spots on the touch screen are pressed. In that case a part of one plate, e.g. the X plate is shorted by the other plate, which decreases the actual plate resistance Vtscbias iplate tspx tsmy tspy tsmx Fig.10 Touch screen setup for plate resistance. The plate resistance measurement is executed in the same way as the pressure resistance measurement. In this case only one of the two plates is biased and the other plate is kept floating. The current through the connected plate is again a direct indication of the connected resistance. 1998 Jul 22 15 Philips Semiconductors Product specification Advanced modem/audio analog front-end UCB1200 TOUCH SCREEN INTERFACE The UCB1200 contains a universal resistive touch screen interface for 4-wire resistive touch screen, capable of performing position, pressure and plate resistance measurements. In addition the touch screen can be programmed to generate interrupts when the touch screen is pressed. The last mode is also active when the UCB1200 is set in the stand-by mode. tspx tsmx tspy tsmy tsc_mode vdda1 touch screen ts..power bias voltage ts..ground touch screen current monitor vssa3 vssa1 tsc_bias_ena adc_input[2:0] analog mux tsc_mode_sel to adc input Fig.11 Block diagram of the touch screen interface. The touch screen interface connects to the touch screen by four wires: TSPX, TSMX, TSPY and TSMY. Each of these pins can be programmed to be floating, powered or grounded in the touch screen switch matrix. The setting of each touch screen pin is programmable through the touch screen control register. Possible conflicting settings (grounding and powering of a touch screen pin at the same time) are detected by the UCB1200. In that case the touch screen pin will be grounded. The UCB1200's internal voltage reference (Vref) is used as reference voltage for the touch screen bias circuit. This makes the touch screen biasing independent of supply voltage and temperature variations. Four low pass filters, one on each touch screen terminal, are built in to minimize the noise coupled from the LCD into the touch screen signals. An LCD typically generates large noise glitches on the touch screen, since they are closely coupled. The influence of the glitches can nevertheless be minimized by performing measurements when the LCD is quiet. This can be done by synchronizing the measurement and the video driver with the ADCSYNC pin. 1998 Jul 22 16 Philips Semiconductors Product specification Advanced modem/audio analog front-end UCB1200 Vdda Rint schmitt trigger tspx tsmy tspy tsmx schmitt trigger Fig.12 Touch screen setup for interrupt detection. In addition to the measurements mentioned above, the touch screen can also act as an interrupt source. In this mode the X plate of the touch screen has to be powered and the Y plate has to be grounded. In this case the touch screen is not biased by the active touch screen bias circuit, but by a resistor to VDDA1. This configuration simply biases the touch screen and the UCB1200 does not consume power unless the touch screen is touched. The voltage on the X plate terminals drops if the screen is pressed. This voltage drop is detected by Schmitt-trigger circuits, of which the outputs are connected to the interrupt control block. A touch screen interrupt is generated either when the touch screen is pressed (falling edge enabled) or when the touch screen is released (rising edge enabled). It can be used to activate the system around the UCB1200 to start a touch screen read-out sequence. The internal Schmitt-trigger circuits are connected to the TSPX and TSMX signals after the built in low pass filters. This reduces the number of spurious interrupts, due to the coupling between the LCD screen and the touch screen sensors. Each of the four touch screen signals can be selected as input for the built in 10 bit ADC, which is used to determine the voltage on the selected touch screen pin. The flexible switch matrix and the multi- functional touch screen bias circuit enables the user of the UCB1200 to set each desired touch screen configuration. The setting of the touch screen bias circuit and the ADC input multiplexer is determined by the setting of TSC_MOD[n] in the touch screen control register according the following table. 1998 Jul 22 17 Philips Semiconductors Product specification Advanced modem/audio analog front-end UCB1200 TOUCH SCREEN MODE SELECTION TSC_MODE[N] SELECTED BITS TOUCH SCREEN BIAS SOURCE ADC MULTIPLEXER SETTING 00 interrupt resistor to VDDA1 defined by ADC_INPUT[n] 01 pressure touch screen bias circuit touch screen current monitor 10 position touch screen bias circuit defined by ADC_INPUT[n] 11 position touch screen bias circuit defined by ADC_INPUT[n] SUMMARY OF TOUCH SCREEN MODES; note 1 TOUCH SCREEN TOUCH TOUCH MEASUREMENT TSPX TSMX TSPY TSMY SCREEN SCREEN MODE BIAS X position powered(2) grounded(2) ADC_INPUT[n] ADC_INPUT[n] position enabled Y position ADC_INPUT[n] ADC_INPUT[n] powered(2) grounded(2) position enabled pressure - 1 powered(2) powered(2) grounded(2) grounded(2) pressure enabled pressure - 2 powered floating grounded floating pressure enabled pressure - 3 floating grounded powered floating pressure enabled pressure - 4 floating powered floating grounded pressure enabled pressure - 5 grounded floating floating powered pressure enabled X-plate resistance powered(2) grounded(2) floating floating pressure enabled Y-plate resistance floating floating powered(2) grounded(2) pressure enabled interrupt powered powered grounded grounded interrupt disabled(3) Notes 1. Control register address 9 is used for touch screen mode selection. 2. The powered and grounded touch screen pins may be interchanged. 3. In this mode, the touch screen bias must be disabled by the user to prevent false interrupts. 1998 Jul 22 18 Philips Semiconductors Product specification Advanced modem/audio analog front-end UCB1200 10 BIT ADC The UCB1200 includes a 10 bit successive approximation analog to digital converter (ADC) with built-in track and hold circuit and an analog multiplexer to select one of the 4 analog inputs (AD0 - AD3), the 4 touch screen inputs (TSPX, TSMX, TSPY, TSMY) or the pressure output of the touch screen bias circuit. The ADC is used to read-out the touch screen inputs and it measures the voltage on the four analog high voltage inputs AD0 - AD3. The analog multiplexer contains 4 resistive dividers to attenuate the high voltage on the AD0 - AD3 inputs to the ADC input range. adcsync internal reference to control reg 11 track&hold 10 mux ADC start adc start 10 bit ADC 9 to 1 stop logic sync enable adc_sync_ena Fig.13 Block diagram of the 10-bit ADC circuit. The ADC is controlled completely through the SIB interface, but the UCB1200 contains internal logic to ease the control of the ADC and to minimize the number of SIB frame read/write actions. A complete ADC control sequence analog to digital conversion consists of several phases. Firstly the ADC has to be enabled, secondly the input selector must be set to the proper input, thirdly the ADC conversion has to be started and finally the ADC result has to be read from register 11. The ADC is activated by setting ADC_ENA in register 10. The ADC circuit, including the track and hold circuit does not consume any power as long as this bit is reset. The analog input multiplexer is controlled by ADC_INPUT[n] and the ADC is actually started with the ADC_START bit. When TSPX and TSMX are in the interrupt mode, the ADC cannot be started, even to measure AD0-3. The UCB1200 has two different modes to start the ADC conversion, which are selected by the ADC_SYNC_ENA bit. The default mode is the non-synchronization mode, in which the conversion is started directly with a 0->1 transition of ADC_START. Secondly the ADC is started at a rising edge of the signal applied to the ADCSYNC pin if ADC_SYNC_ENA is set. The internal track and hold circuit requires a certain settling time to track the input signal correctly. This can be ensured from the software by writing first a SIB frame with the ADC multiplexer setting before the SIB frame with the ADC_START command is transferred. The UCB1200 ADC start/stop logic will detect whether the ADC input multiplexer is changed in the same SIB frame as the ADC start command is given. In that case it will delay the actual start of the ADC circuit to ensure that the track and hold settling time requirements are met. This leads to the following two timing diagrams: 1998 Jul 22 19 Philips Semiconductors Product specification Advanced modem/audio analog front-end UCB1200 tsibwrite tsibwrite tsibwrite `SIB frame' set adc_ena:1 set adc_start:1 set adc_start:0 read adc result tadcena adc_ena (internal) tsamdel1 adc_start (internal) adc_input_selection `adc start state' wait for start wait for start ttrckmin tadcconv `adc state' tracking conversion tracking adc_dat_valid adc_data Fig.14 ADC timing sequence, non ADC sync mode, no changing ADC input multiplexer settings. tsibwrite tsibwrite tsibwrite `SIB frame' set adc_ena:1 set adc_start:1 set adc_start:0 read adc result tadcena adc_ena (internal) tsamdel2 adc_start (internal) adc_input_selection `adc start state' wait for start wait for start ttrckmin tadcconv `adc state' tracking conversion tracking adc_dat_valid adc_data Fig.15 ADC timing sequence, non ADC sync mode, changing ADC input multiplexer settings. The ADC timing diagrams indicate that in the non-ADC sync mode the ADC result can be read in the SIB frame following the SIB frame with the ADC start command, if the ADC multiplexer setting is not changed. If the ADC input multiplexer setting is changed, the ADC result can be read in the second SIB frame following the SIB frame with the ADC start command. 1998 Jul 22 20 Philips Semiconductors Product specification Advanced modem/audio analog front-end UCB1200 The second ADC start mode gives the opportunity to start the ADC at the rising edge of the signal connected to the ADCSYNC pin. The 0->1 transition of the ADC_START bit will arm the ADC, such that it will start in the first detected rising edge of the ADCSYNC signal. Also in this mode, the internal start/stop logic will detect whether the ADC multiplexer settings are changed simultaneously with the ADC start bit and it will add a delay to ensure sufficient setting time for the internal track and hold circuit. A rising edge of the signal connected to the ADCSYNC pin occurring during this tracking time is ignored; the ADC conversion is started on the first rising edge detected after this delay time. This leads to the following two timing diagrams of the ADC conversion. tsibwrite tsibwrite tsibwrite `SIB frame' set adc_ena:1 set adc_start:1 set adc_start:0 read reg:11 tadcena adc_ena (internal) adc_start (internal) adc_input_selection `adc start state' wait for start wait for sync wait for start tadcsam3 tadcconv `adc state' tracking conversion tracking thadcsync adc_sync adc_dat_valid adc_data Fig.16 ADC timing sequence, ADC sync mode, no changing ADC input multiplexer settings. 1998 Jul 22 21 Philips Semiconductors Product specification Advanced modem/audio analog front-end UCB1200 tsibwrite tsibwrite tsibwrite `SIB frame' set adc_ena:1 set adc_start:1 set adc_start:0 read reg:11 tadcena adc_ena (internal) ttrckmin adc_start (internal) adc_input_selection `adc start state' wait for start wait for sync wait for start tadcsam3 tadcconv `adc state' tracking conversion tracking thadcsync adc_sync adc_dat_valid adc_data Fig.17 ADC timing sequence, ADC sync mode, changing ADC input multiplexer settings. The ADC sync mode is particularly useful when the internal ADC has to be synchronized to the external system. Typically it is used to synchronize the read-out of the touch screen to the driving of the LCD screen, which is normally placed beneath the touch screen. Many spikes and a lot of 'noise' are superposed on the touch screen signals, due to the close coupling of the touch screen and the LCD. The result of the conversion is stored in the register 11 of the SIB interface, after the completion of the conversion. An interrupt may be generated whenever a conversion is completed (ADC_FLA_INT and/or ADC_RIS_INT bits in register 2 and 3) to ease the synchronization between the UCB1200 and the system controller. The ADC result is reset to 0x000, whenever the ADC is started or armed till the ADC conversion is completed. ADC_DAT_VAL in the SIB register 11 indicates the status of the ADC; it equals '0' when a ADC sequence is started, which implies that the ADC result is not valid and it equals '1' when the ADC conversion is completed and the result is stored in the SIB register 11. 1998 Jul 22 22 Philips Semiconductors Product specification Advanced modem/audio analog front-end UCB1200 AD[n] adc input MUX ADC_INPUT[n] Fig.18 Block diagram of resistive dividers AD0 - AD3. The applied voltage on the four analog inputs of the UCB1200 (AD0 - AD3) is attenuated before it is applied to the ADC input multiplexer using on chip resistive dividers.These high voltage inputs are optimized to handle voltages larger than the applied supply voltage. The built-in resistive voltage dividers are only activated if the corresponding analog input is selected. The resistive dividers are made floating when the input is not selected by the ADC input multiplexer, such that the input leakage of these high voltage analog pins is minimized. This makes these analog inputs very suitable to monitor battery voltage voltages. 1998 Jul 22 23 Philips Semiconductors Product specification Advanced modem/audio analog front-end UCB1200 ON-CHIP REFERENCE CIRCUIT The UCB1200 contains an on chip reference voltage source, which generates the reference voltages for the 10 bit ADC and the virtual analog ground. Alternatively the UCB1200 can be driven from an external reference voltage source. aud_in_ena aud_out_ena tel_in_ena tel_out_ena tsc_bias_ena adc_en internal ext_vref_ena & analog ground ena internal internal bandgap ADC reference Vbg reference voltage circuitry & vrefbyp_con vrefbyp Fig.19 Block diagram of the reference circuit. The internal reference voltage is connected to the VREFBYP pin, where an external capacitor could be connected to filter this reference voltage, if VREF_CON (register 10) is set. THIS IS NOT RECOMMENDED since the internal impedance of the reference (several 100M ) will be sensitive to board leakage and the turn on time constant will be very long. An external voltage reference connected to the VREFBYP pin is used as voltage reference by the UCB1200 circuit, if the EXT_REF_ENA bit (register 10) is set. Two bits in the ADC control register determine the mode of operation of this reference voltage circuit. VREFBYP_CON connects the internal reference voltage to the VREFBYP pin, while EXT_VREF_ENA disables the internal reference voltage and switches the UCB1200 into the external voltage reference mode. 1998 Jul 22 24 Philips Semiconductors Product specification Advanced modem/audio analog front-end UCB1200 SERIAL INTERFACE BUS The UCB1200 Serial Interface Bus (SIB) is compatible with industry standard serial ports and devices, and is designed to connect directly to a system controller. The SIB protocol allows one or more slave devices to be connected to the system controller. The data transfer is always synchronous and it is frame based. The SIB interface consists of four signals: SIBDIN, SIBDOUT, SIBCLK and SIBSYNC. SIB MASTER UCB1200 sibclk sibclk sibsync sibsync sibdout sibdin sibdin sibdout SIB SLAVE 2 sibclk sibsync sibdin sibdout TO OTHER SIB SLAVES Fig.20 Typical connection between the UCB1200 and the system controller. Each SIB frame consists of at least 64 clock cycles. Typically 128 bits are used, divided into 2 sub frames of 64 bits each. The first word (the bits 0 to 63) is read and/or written by the UCB1200, the remaining bits may be used for communication between the system controller and another slave device. The SIBDOUT pin of the UCB1200 is tri-stated for the bit 64 and higher in the SIB frame to prevent bus conflicts with other slave devices. However when SIB_ZERO (control register 1) is set, the SIBDOUT pin is forced to zero from bit 64 onwards to prevent the SIBDOUT line from floating. This feature is needed when the UCB1200 is the only slave device connected to the bus. The UCB1200 always samples incoming data on the SIBDIN pin on the falling edge of SIBCLK and it outputs data on the SIBDOUT pin on the rising edge of the SIBCLK. The start of a new SIB frame is indicated by a pulse on the SIBSYNC line just before the start of this new SIB frame. 1998 Jul 22 25 Philips Semiconductors Product specification Advanced modem/audio analog front-end UCB1200 bit 0 bit 1 bit 63 bit 64 bit 65 bit 126 bit 127 bit 0 sibclk sibsync sibdin sibdout #1 sibdout #2 Fig.21 Serial data transmission of the UCB1200 The applied clock signal to the SIBCLK pin is used as clock signal inside the UCB1200; all internal clock signals are derived from that. It is required that the SIBCLK signal is applied if one or more analog or digital functions are activated in the UCB1200; only the interrupt controller is implemented asynchronously. SIBCLK may be stopped when all digital and analog functions are disabled; in that case the lowest possible power consumption is met. The SIBCLK should not be stopped during a SIB frame, but only at the end of the SIB-frame, to ensure that all analog and digital functions are stopped properly. Note: The interrupt controller is still active, due to its asynchronous implementation. The UCB1200 can therefore still generate interrupts to the system controller, when the SIBCLK is stopped. The generation of the audio and telecom sample clocks requires that the SIBCLK signal is symmetrical: a non symmetrical SIBCLK will lead to non equidistant sample moments, when an odd frequency divisor is set in either of the audio or telecom control register. 1998 Jul 22 26 Philips Semiconductors Product specification Advanced modem/audio analog front-end UCB1200 SIB DATA FORMAT The first 64 bits in the SIB-frame are read and written by the UCB1200 and they contain both audio and telecom codec data fields, several control bits and a control register data field as is defined in table below. SIB DATA FORMATS SIB FRAME BIT SIBDIN FIELD DEFINITION SIBDOUT FIELD DEFINITION 0 - 11 audio input path data (12 bits); bit 0 = MSB audio output path data (12 bits); bit 0 = MSB 12 - 16 not read but reserved fixed `0' 17 - 20 control register address (4 bits); bit 17 = MSB control register address (4 bits); bit 17 = MSB; is a copy of the register address as present in the SIBDIN field in the same SIB frame. 21 write bit (write 1) fixed `0' 22 - 29 not read but reserved fixed `0' 30 audio valid sample flag audio valid flag 31 telecom valid sample flag telecom valid flag 32 - 45 telecom input path data (14 bits) telecom output path data (14 bits); bit 32 MSB 46 - 47 not read but reserved fixed `0' 48 - 63 control register write data (16 bit); bit 48 = MSB control register read data (16 bit); bit 48 = MSB Since the data transfer is completely synchronous, a given control register may be written many times, before the device feeding the data has a chance to change the control bits. The UCB1200 does detect whether the data is changed or not. CONTROL REGISTER DATA TRANSFER The last 16 bits of the UCB1200 word is made up of control register data. The selection of the control register and whether it is read or written is defined by the control register address field [bit 17:20] and the "write" bit [bit 21]. For a read action on the a control register, the control register address field has to be set to the desired control register address and the "write" bit has to be set to zero in the SIBDIN stream, The read data is sent by the UCB1200 within the control register data field of SIBDOUT during the same frame as the read request occurred. In addition, during a read cycle, the control register data field of SIBDIN is ignored by the UCB1200 which implies that no modifications of the UCB1200 settings can be performed when the "write" bit equals zero in the SIBDIN data-stream. For a write cycle ("write" bit = 1), the control register data contents of SIBDIN are written to the UCB1200 register selected by the register address field after receipt of the complete first word (the update is performed during the 64th bit in the SIB frame). This implies that the control register data contents of SIBDOUT data-stream in a SIB frame represents the previous contents of the selected control register. The control register address in the SIBDOUT data-stream is a copy of the selected control register in the SIB data-stream. These bits show an additional delay since they pass additional circuit in the UCB1200. The control register data is actually written in the control registers after the transfer of the first SIB word is completed. This implies that the control register data is updated during bit 64 of the SIB frame. The control data is only updated when the write bit is '1' in the SIB frame. The control data will not be updated when the write bit equals '0'. This simplifies the read out of control register data, since it is not required to send 'valid' data in the control register data field when a control register is read, if the write bit is kept at '0'. 1998 Jul 22 27 Philips Semiconductors Product specification Advanced modem/audio analog front-end UCB1200 bit 63 bit 64 bit 65 bit 66 tpcdu sibclk sibsync sibdin control data Fig.22 Control register update timing. The control register data in the SIBDOUT stream is sampled just before the SIB frame is started. This implies that the returned control register data represents the 'old' control data, in case new data was provided in the SIBDIN data stream. tsibclk tpcldo tsclsy thclsy tscldi thcldi sibclk sibsync tpdido sibdin sibdout Fig.23 Timing definitions SIB interface 1998 Jul 22 28 Philips Semiconductors Product specification Advanced modem/audio analog front-end UCB1200 GENERAL PURPOSE I/O The UCB1200 has 10 programmable digital input/output (I/O) pins. These pins can be independently programmed as input or output using IO_DIR[0:9] in control register 1. The output data is determined by the content of IO_DATA[n] in control register 0, while the actual status of these pins can be read from the IO_DATA[n] bits in control register 0. IO_DIR[n] IO_DATA[n] (Write) IO[n] IO_DATA[n] (Read) to interrupt module Fig.24 Block diagram of I/O pin circuit. The data on the IO0-IO9 pins are feed into the interrupt control block, where they can generate an interrupt on the rising and/or falling edge of these signals. 1998 Jul 22 29 Philips Semiconductors Product specification Advanced modem/audio analog front-end UCB1200 INTERRUPT CIRCUIT The UCB1200 contains a programmable interrupt control block, which can generate an interrupt for a '0' to '1' and/or a '1' to '0' transition on one or more of the IO0-IO9 pins, the audio and telecom clip detect, the adc_ready signal and the TSPX and TSMX signals. The interrupt generation mode is set by IO_RIS_INT[n] in register 2 and INT_FAL_ENA[n] in control register 3. The actual interrupt status of each signal can be read from the control register 4. The interrupt status is cleared whenever a `0' to `1' transition is written in control register 4 for the corresponding bit. rising edge interrupt enable `1' D Q register 2 `OR' tree interrupt source & R IRQOUT D Q & R falling edge interrupt enable interrupt status register 3 register 4 (read) interrupt clear reset register 4 (write) Fig.25 Block diagram of the interrupt controller. The IRQOUT pin presents the 'OR' function of all interrupt status bits and can be used to give an interrupt to the system controller. The interrupt controller is implemented asynchronously. This provides the possibility to generate interrupts when the SIBCLK is stopped, e.g. an interrupt can be generated in power down mode, when the touch screen is pressed or when the state of one of the IO pins changes. 1998 Jul 22 30 Philips Semiconductors Product specification Advanced modem/audio analog front-end UCB1200 RESET CIRCUIT RESET is captured in the UCB1200 using a asynchronous pulse stretching circuit. RESET may be pulled down when the SIBCLK is still stopped. The internal circuit remembers this reset signal and generates an internal reset signal for at least 5 SIBCLK periods. & COUNT internal `1' D Q D Q D Q <3 reset R R RESET SIBCLK Fig.26 Block diagram of the reset circuit. sibclk tlnrst trsti nreset arstn count 0 1 2 3 internal reset Fig.27 Timing diagram of the reset circuit. 1998 Jul 22 31 Philips Semiconductors Product specification Advanced modem/audio analog front-end UCB1200 POWER ROUTING STRATEGY The UCB1200 has nine power supply pins, since the UCB1200 contains five power supply regions within the circuit. The analog and digital parts have their separate power supplies to reduce the interference between these parts. The speaker driver circuit is powered separately (VDDA2/VSSA2) from the other analog circuit parts and the touch screen switch matrix has its own ground pin (VSSA3). This separation in the analog part reduces the interference between the speaker driver and the touch screen switch matrix, which has relatively large and fluctuating current consumption and the remaining parts of the analog circuit. 32 48 vddd vddd vdda1 17 UCB1200 vdda2 10 3.3V supply 7 vssa2 vssa3 vssd vssd vssa1 26 37 5 18 Fig.28 Recommended power supply connection strategy, single power supply systems. 1998 Jul 22 32 Philips Semiconductors Product specification Advanced modem/audio analog front-end UCB1200 32 48 vddd vddd vdda1 17 UCB1200 vdda2 10 3.3V analog supply 3.3V digital supply 7 vssa2 vssa3 vssd vssd vssa1 26 37 5 18 Fig.29 Recommended power supply connection strategy, dual power supply systems. The VSSD pins and the VSSA1 pin are connected within the UCB1200 circuit. It is recommended to connect the VSSD pins and the VSSA1 directly to a ground plane on the PCB. The split in power supply connections should be maintained on the PCB to get optimal separation. Fig.28 shows the recommended PCB power supply strategy if only one single supply is used, while Fig.29 shows the recommended power supply connection for a dual power supply system, with separate analog and digital supplies. 1998 Jul 22 33 Philips Semiconductors Product specification Advanced modem/audio analog front-end UCB1200 APPLICATION INFORMATION In this chapter some application information is contained. More information will be available when an Application Note on UCB1200 is published. Sidetone suppression circuit UCB1200 TOUTP 11 Ro Rg TINP 1:1 transformer Ri 15 - A Rt Rt Rs + + Rt Rt Rs B 14 Ri - TINN Rg Ro 12 TOUTN Fig.30 Typical telecom codec sidetone suppression circuit (without protection circuits). An important built-in feature of the telecom codec is the sidetone suppression circuit. The sidetone suppression circuit is activated when TEL_SIDE_ENA in the telecom control register B is set. The telecom input signal contains a large part of the telecom output signal, when the sidetone suppression circuit is disabled. The available dynamic range of the telecom input is occupied largely by the telecom output voltage. The sidetone suppression circuit subtracts a part of the telecom output signal from the telecom input signal when activated. The available dynamic range is in that case used more effectively than without sidetone suppression. The built in side tone suppression circuit, shown in Fig.30, has a fixed subtraction ratio, set be the resistors Rs and Ri, which equals 600/456. This ratio is calculated from the following relations. The impedance seen by the telephone line equals: R × Z o Ri = + + ------------------- × , line 2 Rt Rt R 0 + Ri in which Rt represents winding resistance of the transformer, divided by 2. Assuming Ri >> Ro then Rline = Rt + Rt + Ro = 600 2 = 300 1998 Jul 22 34 Philips Semiconductors Product specification Advanced modem/audio analog front-end UCB1200 A typical transformer has 156 winding impedance, thus Ro should be 144 . The ratio of the telecom input and output voltage is therefore: V 156 + 300 456 i(tel) = Vo(tel) × = × 156 + 300 + 144 ------------------------------------------ Vo(tel) 600 ---------- 1998 Jul 22 35 Philips Semiconductors Product specification Advanced modem/audio analog front-end UCB1200 Codec data transfer The UCB1200 codec operates at samples which depend on the applied SIBCLK frequency and the programmed audio and telecom divisors. The codec data transfer between the UCB1200 and the system controller has to be synchronized with the UCB1200 sample counters and the SIB bus data transfer protocol to prevent conversion errors, resulting in high distortion. Correct codec data transfer is obtained easily when the UCB1200 is connected to one of the controllers in the PR3000 series, but the UCB1200 can also be connected to other controllers, if the following data protocol is used. START OF CODEC DATA TRANSFER The UCB1200 internal sample counters are started at the beginning of the first SIB frame following the SIB frame in which the codec input and/or output path is enabled. This implies that the sample rate divisor has to be programmed before the codec input and/or output path is enabled, Fig.31. Changing the sample rate on the fly, that is without disabling both the codec input and output path before the divisor is reprogrammed, will disturb the codec data transfer synchronization between the UCB1200 and its controller and is therefore not allowed. ADCSYNC SIBDIN reg. 5 or 7 reg. 6 or 8 sample counter 0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8 0 1 2 sample frequency Fig.31 Start-up sequence of the codec, TEL_DIV[n] = 9. 1998 Jul 22 36 Philips Semiconductors Product specification Advanced modem/audio analog front-end UCB1200 CODEC DATA TRANSFER INTO THE UCB1200 Both the audio and the telecom data is transferred within the SIB frame (bit 11-0 and bit 47-32). This data is accompanied by two data valid flags (bit 30: audio data valid, bit 31: telecom data valid). The codec data in the SIB frames is only processed in the UCB1200 if the appropriate data valid flag is set in the frame; the data is discarded when the data flag equals `0'. Figure 32 shows the basic codec data synchronization principle used in the UCB1200. SIB INTERFACE UPSAMPLE FILTERS audio data[n] SIBCLK DFF input latch audio_data_valid & SIBDIN fsa SIBSYNC telecom data[n] 64 bit shift register DFF input latch telec_data_valid & bit64 fst Fig.32 Codec input path data synchronization principle. Figure 32 shows that audio and telecom data is made available for the codec up sample filters during the 64th bit in the SIB frame. This implies that the codec data has to be transferred in one of the SIB frames preceding the codec sample moment. Note: If the programmed divisor equals a multiple of 4, the codec data transfer is synchronized to the SIB frame repetition rate (e.g. AUD_DIV[n] = 8 1 sample is needed in 2 SIB frames, AUD_DIV[n] = 12 1 sample is needed in 3 SIB frames, etc.). 1998 Jul 22 37 Philips Semiconductors Product specification Advanced modem/audio analog front-end UCB1200 CODEC DATA TRANSFER FROM THE UCB1200 The data resulting from the UCB1200 codec ADC (input) paths is transfer to the system controller at the programmed codec sample rate. However the codec data is synchronized with the SIB frame repetition rate. Figure 33 shows the basic synchronization principle used inside the UCB1200. Codec data will be present in each SIB frame produced by the UCB1200; the sample will be repeated in the following SIB frames till a new sample has become available. DOWN SAMPLE FILTERS SIB INTERFACE audio data[n] output load SIBCLK DFF latch bit0 SIBDOUT fsa bit21 telec data[n] SIBSYNC output load 64 bit shift register DFF latch bit48 fst bit21 Fig.33 synchronization of codec samples in SIBDOUT data stream. The codec samples in the SIBDOUT stream are also accompanied by a audio and telecom data valid bit (bit 30 and bit 31). These data valid flags are zero if the corresponding codec adc paths are disabled and during the start up period of the codec's, when unreliable samples are generated. By default (after reset), the data valid bits will be continuously `1' when reliable samples are generated. However when DYN_VFLAG_ENA is set, the data valid bits will be `1' during one of the SIB frames, containing identical samples (this is the case when a high divisor is programmed). The audio_vflag bit will be high during the last sample in a series of identical samples, while the telecom_vflag bit is high at the first sample in a series of identical bits. An example of the timing diagram is shown in figure 34. SIBSYNC fsa audio codec out sample N sample N+1 sample N+2 sample N+3 SIBDOUT sample N sample N sample N+1 sample N+1 sample N+2 sample N+2 sample N+2 sample N+3 audio_vflag bit Fig.34 Audio codec data transfer, AUD_DIV[n] = 9, DYN_VFLAG_ENA = 1. 1998 Jul 22 38 Philips Semiconductors Product specification Advanced modem/audio analog front-end UCB1200 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134); notes 1 and 2 SYMBOL PARAMETER MIN. MAX. UNIT VDD supply voltage -0.5 +5.0 V VI DC input voltage (except inputs AD0 - AD3) -0.5 VDD + 0.5 V VI DC input voltage AD0 - AD3 -0.5 +8.5 V VO DC output voltage - VDD + 0.5 V II(d) diode input current - 10 mA IO(d) diode output current - 10 mA IO continuous output current, digital outputs - 4 mA Tstg storage temperature -55 +150 °C Notes 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the Absolute Maximum Rating section of this specification is not implied. 2. Parameters are valid over the ambient operating temperature unless otherwise specified. All voltages are with respect to VSSD (pin 37), unless otherwise noted. THERMAL CHARACTERISTICS SYMBOL PARAMETER VALUE UNIT Rth(j-a) thermal resistance from junction to ambient in free air 67 K/W 1998 Jul 22 39 Philips Semiconductors Product specification Advanced modem/audio analog front-end UCB1200 DC CHARACTERISTICS VSSD = VSSA1 = VSSA2 = VSSA3 = 0 V; Tamb =25 °C; fi(sibclk) = 9.216 MHz; VI(ref) = 1.2 V; all voltages referenced to VSSD (pin 5); unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VDDD digital supply voltage 3.0 3.3 3.6 V VDDA1 analog supply voltage - excl. 3.0 3.3 3.6 V speaker driver VDDA2 analog supply voltage - 3.0 3.3 3.6 V speaker driver only VSSA2 analog ground - speaker driver -0.4 0 +0.4 V VSSA3 analog ground - touch screen -0.4 0 +0.4 V switch matrix IDDD digital supply current(1) full functionality - 19 - mA only audio codec activated - 17 - mA only telecom codec activated - 19 - mA only touch screen activated - 15 - mA only ADC activated - 15 - mA no functions activated; fsibclk - - 10 µA off IDDA1 analog supply current(1)(2) full functionality - 4.6 - mA only audio codec activated - 3.7 - mA only telecom codec activated - 4.4 - mA only touch screen activated - 1.0 - mA only touch screen in interrupt - - 100 µA mode only ADC activated - 1.0 - mA no analog functions activated - <10 - µA IDDA2 total speaker driver supply(1)(2) speaker driver enabled - 0.6 - mA current speaker driver disabled - - 10 µA VIL LOW level input voltage -0.5 - +0.3VDDD V VIH HIGH level input voltage 0.7VDDD - 0.5VDDD V VOL LOW level output voltage IOL = 2 mA - - 0.2VDDD V VOH HIGH level output voltage IOH = 2 mA 0.8VDDD - - V fi(sibclk) serial interface clock frequency 0 10 15 MHz Tamb operating ambient temperature -20 - 70 °C Notes 1. Indicative value measured during the initial characterization. 2. Excluding connected touch screen and speaker load currents. 1998 Jul 22 40 Philips Semiconductors Product specification Advanced modem/audio analog front-end UCB1200 AC CHARACTERISTICS VSSD = VSSA1 = VSSA2 = VSSA3 = 0 V; VDDD = VDDA1 = VDDA2 = 3.3 V+/-10%; Tamb =25 °C; VI(ref) = 1.2 V; fi(sibclk) = 9.216 MHz; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Audio Input; notes 1 and 2 fsa audio sample frequency - - 26 kHz VI(RMS) input voltage (RMS value) 0 dB gain setting 90 100 125 mV VI(BIAS) DC bias voltage MICP input 1.35 1.4 1.5 V Zi input impedance 20 25 - k Z(18-20) impedance MICGND - - - 200 VSSA1 Gstep gain step size 1 1.5 2 dB Nstep number of gain settings - 32 - - Gv gain (AUD_GAIN=011111) 15 22.5 28 dB EG gain error each gain step -1 - 1 dB RES resolution - 12 - bit LE(d)(ADC) ADC differential linearity - - 1 LSB error THD total harmonic distortion input gain = 0 dB - - -40 dB (AUD_GAIN = 00000); input signal = 1 mVrms - - -26 dB input gain = 22.5 dB (AUD_GAIN[n] = 01111); AC coupling enabled (AUD_OFF_CAN = 1); S/N signal-to-noise ratio input gain = 0 dB 50 - - dB (AUD_GAIN = 00000) input signal = 1mV (RMS); 25 - - dB input gain = 22.5 dB (AUD_GAIN[n] = 01111); PBRR pass-band ripple rejection fpla < fsig < fpha(3) - - 1.2 dB SBR stop-band rejection fsha < fsig < 20 kHz(3) 50 - - dB Doffset digital offset no signal applied to MICP - - 50 LSB Audio Output; notes 4 and 5 VO(RMS) output voltage (RMS attenuation = 0 dB, 1.0 1.25 1.5 V value) differentially measured between SKPRN and SPRKP Eoffset offset error (peak-to-peak - - 100 mV value) VO(BIAS) DC bias voltage SPKRP/SKPRN 1.2 1.4 1.6 V step attenuation step size 2.5 3.0 3.5 dB (analog section) Nstep number of attenuation - 24 - - steps 1998 Jul 22 41 Philips Semiconductors Product specification Advanced modem/audio analog front-end UCB1200 SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT attenuation 63 69 75 dB RES resolution - 12 - bit LE(d)(DAC) DAC differential linearity - - 1 LSB error THD total harmonic distortion - - -35 dB 1 k headphone load - - -45 dB S/N signal-to-noise ratio 16 speaker; 100 Hz to 40 - - dB 20 kHz bandwidth PBRR pass-band ripple rejection fpla < fsig < fpha(6) - - 1.2 dB SBR stop-band rejection fsha < fsig < 20 kHz(6) 50 - - dB OBR(RMS) out-of-band rejection f > 20 kHz - - 50 mV (RMS value) Zspeaker speaker impedance 8 16 - Telecom Input; notes 2 and 7 fst sample frequency - - 10 kHz VI(RMS) input voltage (RMS value) differentially applied to 330 370 410 mV TINN and TINP; no I/P attenuation enabled (TEL_ATT = 0) VI(BIAS) DC bias voltage TINN/TINP 1.2 - 1.6 V i input attenuation input attenuation enabled 5.5 6 6.5 dB (TEL_ATT = 1) Zi input impedance 25 - - k S/N signal-to-noise ratio 65 75 - dB THD total harmonic distortion - -76 -65 dB LE(d)(ADC) ADC differential linearity - - 2 LSB error RES resolution - 14 - bit PBRR pass-band ripple rejection fplt < fsig < fpht; no voice - - 1.2 dB filter(8)(16) fvht < fsig < fpht; voice filter - - 1.2 dB activated(8)(16) SBR stop-band rejection fsig < fvlt; voice filter 30 - - dB activated(8)(16) fsht < fsig(8)(16) 50 - - dB Doffset digital offset no signal applied to MICP - - 50 LSB Ssup sidetone suppression 600 line impedance; 1:1 20 - - dB effectiveness transformer with 156 winding resistance Telecom output; note 5 fst sample frequency - - 10 kHz 1998 Jul 22 42 Philips Semiconductors Product specification Advanced modem/audio analog front-end UCB1200 SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VO(RMS) output voltage (RMS differentially measured 1.35 - 1.85 V value) between TOUTP and TOUTN VO(BIAS) DC bias voltage TOUTP/TOUTN; telecom 1.2 - 1.6 V O/P path enabled RES resolution - 14 - bit S/N signal-to-noise ratio 65 75 - dB THD total harmonic distortion - -76 -65 dB PBRR pass-band ripple rejection - - 1.2 dB SBR stop-band rejection fsht < f < fst(9) 70 - - dB OBR(RMS) out-of-band rejection f > fst(9)(16) - - 25 mV (RMS value) Zo(load) load impedance 600 Eoffset offset error note 10 - - 100 mV Touch screen VI(BIAS) bias voltage touch screen position 1.6 1.8 2.0 V mode selected I touch screen current touch screen position 10 - - mA mode selected Ri Max. touch screen touch screen interrupt - - 2500 resistance to generate an mode selected interrupt Rgs ground switch on - - 50 resistance Rps power switch on - - 50 resistance tSTRTU start up time of touch - - 25 µs screen bias voltage generator Eidle Idle pressure reading pressure mode selected, 40 120 LSB open (no current drawn) ligth_touch Pressure reading: pressure mode selected, 65 LSB light-touch - 1.5xEidle(18) 2.2k for light touch, open for idle Rpres pressure mode full scale 300